ASIC verification engineer needed +++

ASIC Verification Engineer (Ottawa)

.. Minimum 4 years experience with Vera, Specman or SystemVerilog (current
environment in Veraa nd future projects will be migrating, possibly
SystemVerilog)
.. Experience in development of Bus Functional models (BFMs) and checkers
using VERA
.. Minimum 4 years experience with Verilog Simulators & Waveform Debugging
tools (esp. Synopsys VCS)
.. Experience with SPI bus protocol, specifically in the verification of
peripherals (Flash, EEPROM)
.. Working knowledge of Verilog/VHDL RTL (at least 4 yrs of experience)
.. Familiarity with use of Hardware assertions (i.e. SystemVerilog
Assertions)
.. Experience in scripting languages (i.e.: C-shell, Perl, Python, TCL)

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